Figure 1: Simultaneous Sizing and Restructuring Figure 2: Two Alternative 4-input nor Structures Figure 3: Optimal Sizing for Two 4-input nor Structures

We describe a fast (linear time) procedure to optimally size transistors in a chain of multi-input gates/stages. The fast sizing is used in a simultaneous sizing and restructuring optimization procedure, to accurately predict relative optimal performance of alternative circuit structures for a given total area. The idea extends the concept of optimally sizing a buffer chain[5], and uses tapering constants based on the position of a stage in a circuit, and the position of a transistor in a stack. Transistor and gate sizing for optimal area/delay trade-off is a well explored problem[1-4]. Sensitivity based iterative approaches and linear/non-linear programming techniques have been proposed. These methods assume a fixed circuit structure and hence become unsuitable for situations, like in [6], where both the structure and the device sizes in a circuit are simultaneously modified for improved optimization. In [6], a sensitivity-based iterative sizing is done in several steps, while the circuit itself is being restructured between the steps, as shown in Figure 1. The restructuring is done on a set of subcircuits (called windows) which together cover the critical path. This phase involves generating a large number of alternative windows having different logical and transistor level structure than the original windows, trial sizing the circuit with each candidate replacement, and selecting the ones that lead to the best performance for the circuit area at that stage. The dotted curves in Figure 1 arise as alternative windows are inserted at minimum size, and then sized up optimally to current total size. Since several hundreds of structural alternatives may be generated for each window, evaluating all of them by trial sizing the circuit with each one of them will be computationally prohibitive if methods such as [1-4] are employed. Figure 1: Simultaneous sizing and restructuring We describe below a fast (linear time) sizing procedure that evaluates alternative structures for their performance at a target total area. On inserting the best structure so predicted, the final sizing for that step can be done by a more accurate method[1-4]. Consider the two alternative 4-input NOR structures shown in Figure 2. Figure 2: Two alternative 4-input NOR structures In Figure 3, curves Sa and Sb show the optimal sizing trade-off generated by an accurate sensitivity based procedure, for the structures (a) and (b) in Figure 2, respectively. Note the cross-over point of these curves, demarcating two regions (total area) in which different structures depict better performance relative to the other. Therefore, in comparing two structures for speed at a given area, it is not necessary to have their exact sizing trade-off (i.e. curves Sa and Sb), but rather some approximate sizing behavior that accurately captures the cross-over point would do. This is the basic goal of the fast sizing procedure described below. In fact, the curves Ca and Cb in Figure 3 are the optimal trade-off for the respective structures, generated using the proposed fast sizing technique. Note the accuracy with which the cross-over point is predicted. Figure 3: Optimal sizing for two 4-input NOR structures It is shown in [5] that, under certain assumptions, the ratio of sizes of successive stages (called stage tapering ratio) in an optimal buffer chain is constant (equal to e), and that the optimal number of stages is uniquely determined by output load and the ratio of drain to gate capacitances of a unit buffer. The consequence of this result is that the task of sizing the buffers in a chain (presumably with optimal number of stages) reduces simply to one of allocating the total area among the stages based on the tapering ratio, without a need to consider sensitivities. Our main idea is to extend this basic result to a chain of multi-input gates/stages of arbitrary length, so that optimal sizes of stages, and optimal sizes of transistors within